Zen 4 will be huge!

[dangi12012]

A quick glance into the details of Zen4:
https://en.wikichip.org/wiki/amd/microa ... ures/zen_4

unveils that the Galois Field Instructions are available.
This means that in the future you can matrix multiply a Bitboard with another Bitboard!
Binary Matrix multiplication is infinitely more useful than any instruction we got in computerchess so far.


Among other things this means that the extended Hyperbola Qsc. Algorithm will be solvable in 4 rays at once (4x64bit Bitrotation)
And staying in 256 Instrinsics code the whole time!

Code: Select all

return ((o - bit) ^ bit_reverse(bit_reverse(o) - bit_rev)) & mask;

https://github.com/Gigantua/Chess_Moveg ... tation.hpp
Because bit reversal of 64 bits can be done with binary 64bit matrix multiplication.

So reverse bits, directly calculatingthe moveset etc. should all be possible to implement with the Galois Field instruction set.

Also AVX512 BF16 is more versatile than just using just AVX2.
All in all a very interesting step in the right direction

[Modern Times]

No doubt "magnum" will come along soon to tell us that Apple is already a million times better.

[Joost Buijs]

A quick glance into the details of Zen4:
https://en.wikichip.org/wiki/amd/microa ... ures/zen_4

unveils that the Galois Field Instructions are available.
This means that in the future you can matrix multiply a Bitboard with another Bitboard!
Binary Matrix multiplication is infinitely more useful than any instruction we got in computerchess so far.


Among other things this means that the extended Hyperbola Qsc. Algorithm will be solvable in 4 rays at once (4x64bit Bitrotation)
And staying in 256 Instrinsics code the whole time!

Code: Select all

return ((o - bit) ^ bit_reverse(bit_reverse(o) - bit_rev)) & mask;

https://github.com/Gigantua/Chess_Moveg ... tation.hpp
Because bit reversal of 64 bits can be done with binary 64bit matrix multiplication.

So reverse bits, directly calculatingthe moveset etc. should all be possible to implement with the Galois Field instruction set.

Also AVX512 BF16 is more versatile than just using just AVX2.
All in all a very interesting step in the right direction

I wonder if it is as good as you think it is. The AVX-512 data path is only 256 bits, and AMD has the habit of implementing complex instructions in microcode. Just 2 memory channels seem a bit meager too.

I decided not to buy one, and to wait for either the Zen4 Threadripper (Pro) or the new Intel SPR Xeon.

[Werewolf]

If it's Genoa you're waiting for, the EPYCs are nearly here. Threadripper Genoa will be at least another year or so.

[Ras]

What will also be huge with Zen4 is the power draw: 230W for the 12/16 core models. That's not far from Intel's ridiculous 241W with the 12900K.

[Vinvin]

Here's the video of yesterday presentation (that I already posted in another thread) :

[Modern Times]

What will also be huge with Zen4 is the power draw: 230W for the 12/16 core models. That's not far from Intel's ridiculous 241W with the 12900K.

There are a lot of different numbers being bandied about, I'd wait for real-world numbers once the reputable testing websites and youtube channels put retail units through their tests suites.

[Ras]

There are a lot of different numbers being bandied about, I'd wait for real-world numbers once the reputable testing websites and youtube channels put retail units through their tests suites.

Up to now, AMD's PPT (which is TDP * 1.35) was accurate under full load, provided that the cooling is sufficient to avoid thermal throttling.

But hey, Intel's 13th gen is claimed to ramp up to 350W peak. Throw in a 450W+ Nvidia 4000 series, account for GPU power spikes, and even a 1kW PSU won't be enough. Folks in the US with 110V will need a dedicated wall power circuit just for the PC alone. Totally crazy.

[Chessqueen]

There are a lot of different numbers being bandied about, I'd wait for real-world numbers once the reputable testing websites and youtube channels put retail units through their tests suites.

Up to now, AMD's PPT (which is TDP * 1.35) was accurate under full load, provided that the cooling is sufficient to avoid thermal throttling.

But hey, Intel's 13th gen is claimed to ramp up to 350W peak. Throw in a 450W+ Nvidia 4000 series, account for GPU power spikes, and even a 1kW PSU won't be enough. Folks in the US with 110V will need a dedicated wall power circuit just for the PC alone. Totally crazy.

We are getting closer and closer in solving chess or at least NOT losing when playing White with the top 2 engines with regular PC WOW

[chrisw]

A quick glance into the details of Zen4:
https://en.wikichip.org/wiki/amd/microa ... ures/zen_4

unveils that the Galois Field Instructions are available.
This means that in the future you can matrix multiply a Bitboard with another Bitboard!
Binary Matrix multiplication is infinitely more useful than any instruction we got in computerchess so far.


Among other things this means that the extended Hyperbola Qsc. Algorithm will be solvable in 4 rays at once (4x64bit Bitrotation)
And staying in 256 Instrinsics code the whole time!

Code: Select all

return ((o - bit) ^ bit_reverse(bit_reverse(o) - bit_rev)) & mask;

https://github.com/Gigantua/Chess_Moveg ... tation.hpp
Because bit reversal of 64 bits can be done with binary 64bit matrix multiplication.

So reverse bits, directly calculatingthe moveset etc. should all be possible to implement with the Galois Field instruction set.

Also AVX512 BF16 is more versatile than just using just AVX2.
All in all a very interesting step in the right direction

I wonder if it is as good as you think it is. The AVX-512 data path is only 256 bits, and AMD has the habit of implementing complex instructions in microcode. Just 2 memory channels seem a bit meager too.

I decided not to buy one, and to wait for either the Zen4 Threadripper (Pro) or the new Intel SPR Xeon.

NightmareX vs ChessSystemTalX on 96 cores each in 2022