Tapered Eval between 4 phases

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Re: Tapered Eval between 4 phases

Post by ymatioun » Mon Oct 16, 2017 9:50 pm

I tried this earlier this year; i tried using 4 stages, 8 stages and even 16 stages (you can fit 16 16-bit values into one AVX variable that you can operate on in one instruction, so up to 16 stages can be accommodated with virtually no performance penalty). This significantly reduces variance of the residual in optimization(possibly due to overfitting), but i could not get any performance improvement.

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