History of Memory Wall in Computer Chess?

[smatovic]

Maybe to clarify on what confused me, the Amiga 500 with 68k and custom chips
for example...

- CPU clock of 7.14 MHz
- memory bus clock of 3.57 MHz
- 260 ns DRAM chips

The 68000 CPU needs 4 clock cycles for an memory fetch, hence the CPU memory bus
ran effective with 1.785 MHz, but the chip RAM on board is clocked higher for
the graphics co-processor, it had the DMA processor Agnus on board which was able
to run memory bus at 3.57 MHz....further, the Amiga systems have support for
additional slow and fast RAM, both for CPU only.

--
Srdja

[smatovic]

Okay, so the 386/486/586 CPUs ran at higher clocks than main memory and had L1 resp. L2 cache of maybe 256KB on the motherboard, but what about the Motorola 68k series for example?

In Wikipedia specs for the last Amiga model, the A4000, I see a clock rate for the 68040 of 25 MHz, but no L2 cache, so the RAM was here 'hot-clocked' with the CPU/MMU? What about higher clocked 68ks resp. later models like 68060? Did the RAM frequency catch up, or did they add L2 cache on the mother/accelerator-boards?

--
Srdja

Okay, after some web research I see that it is not that easy...I mixed up memory
access latency measured in ns with memory bus clock and ignored CPU memory wait
states and pipelines...


--
Srdja

Followup...

- Motorola's 68030 internal MMU had support for external L2 cache.

- Amiga 4000 with 68040@25 MHz had 80ns (12.5 MHz) or 60ns Fast RAM, CPU memory fetch cycle was one clock, makes sense to me.

- Several 68060 accelerator boards with 50+ MHz had build in or upgradeable L2 cache on board.

Again, topic solved.

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Srdja