Maybe a new use case for an old idea of mine

[Michael Sherwin]

You make it sound like there is any shared storage between the orphaned cores and the others. But if that were true, they would certainly also share the memory interface. Data is either in one groups of cores or in the other, and the one where it isn't just has tough luck when it wants to access it, because then it will have to be transferred over a 'slow' connection. This is why the access to memory from the orphaned cores is slow in the first place. It adds the (two-way) transfer time between the groups to the memory access time.

I see the problem that you are alluding to. The scheme is still accessing main memory for each store and retrieval. Although it is a small area I do not know how that small area gets to the memory cache. Does it change in the memory cache when it changes in the main memory or when it is accessed and has been marked invalid? I have no idea how that is done so I cannot comment further on that issue.

However, for someone that already has an smp engine it would take very little time to test and make a report.

[hgm]

Well, as a disclaimer let me confess I know nothing about this particular chip. But I know a lot about how these CPUs are designed in general. What you describe suggests that this is actually two independent chips in one package. Electrically that would be like a dual-socket mother board, except that communication between the chips can now be a lot faster than when it has to be routed to another package over the mother board. (The old Pentium Pro had such a design with a CPU chip and a separate level-2 cache chip in one package.)

In general a modern CPU chip has its own memory controller, which communicates with a highest-level cache (on Intel i7 that is level 3, I don't know for AMD). This cache is shared by all cores on the chip, and automatically retains copies of all memory that was read for as long as it can. And if one of the cores writes to memory it only goes in the cache, and the memory is not touched (so it now contains obsolete, faulty data). The memory is only updated when the 'dirty' cache line has to be replaced by more recent stuff ('write-back'). So that cache can be used for fast transfer between cores of the same chip.

A bus connection between the chips in a multi-CPU configuration is used to allow the memory controller in one chip to peek into the cache of all other chips at the same time as accessing its private memory through its own controller; if a 'dirty' line is found the memory access is aborted (as it will be no good), and the CPU that has the valid data in cache will send it on the inter-CPU bus to the CPU that requested it. The latter than will take that instead of the memory.

I suppose this all happens automatically when CPU A requests data from an address that is located in the memory controlled by CPU B; the memory controller of A will then (after translating virtual memory address to physical memory address) abort its memory access for that reason, even if it is not in any cache of CPU B, and will then trigger a memory fetch in CPU B to get it there. Once it arrives in CPU B this will then send it to CPU A through the inter-CPU connection.

[Modern Times]

Well, as a disclaimer let me confess I know nothing about this particular chip. But I know a lot about how these CPUs are designed in general. What you describe suggests that this is actually two independent chips in one package. Electrically that would be like a dual-socket mother board, except that communication between the chips can now be a lot faster than when it has to be routed to another package over the mother board. (The old Pentium Pro had such a design with a CPU chip and a separate level-2 cache chip in one package.)

As a disclaimer, this is all way too technical for me ! But yes HG that is my understanding of this chip. It is effectively NUMA within a single socket rather than NUMA across two sockets.

(The old Pentium Pro had such a design with a CPU chip and a separate level-2 cache chip in one package.)

I had one of those Ran OS/2 on it at the time.