For the Hardware Experts:FSB 1333 and its influence on speed

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Lombard

For the Hardware Experts:FSB 1333 and its influence on speed

Post by Lombard »

For Intel- processors the new fsb- (front side bus) frequency is on the horizon. To the already existing P35 chipset for motherboards Intel added today new processors (see for ex. "Daily Tech") which ar able to work with this fsb-rate.
Can anyone assess what will be the effect on integer based chessprograms?
Will this accelerate the access to hashtables?
Will the mp-comunication dramtically be increased?
Or will the effect be rather marginal as benchmarks for floatingpoint based programs indicate? :?: :?: :?:
CRoberson
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Re: For the Hardware Experts:FSB 1333 and its influence on s

Post by CRoberson »

Performance improvements in one area of a machine do not effect
the speed of all types of programs in consistant ways.

It all depends on where the bottleneck is for each type of program.
For instance, if a programs performance bottleneck is in the cpu
itself, then an improvement in FSB may do little.

On the other hand, if the bottleneck is in memory access (as in
multiprocessor chess programs (4 or more procs)), then speeding
up the processor is likely to do little. However, speedup in the memory
access should make a noticable improvement unless Intel cuts the
size of the cache or moves the cahce off chip. They've done that
before.
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hgm
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Full name: H G Muller

Re: For the Hardware Experts:FSB 1333 and its influence on s

Post by hgm »

Hard to say. The FSB rate determines how fast data can be shuttled between the DPU and the north bridge of the chip set (containing the DRAM controller).

But the main bottleneck to DRAM access is usually the memry controller or the DRAM itself. How long it takes to retrieve the data after issuing the address is not dependent on FSB speed, and sually takes many FSB cycles.

DRAM is divided in banks, and banks consist of pages. In each bank a limited number of pages can be 'open', and access to data in such an open page is far faster than to other data. But closing a page takes extra time. Meory bandwidth and latency is much more determined by how clever the memory controller is to close pages it thinks are no longer needed, and overlap memory transactions to make the most out of the north-bridge to DRAM bus.

And to circumvent the bottleneck of this latter bus, there can be several banks of memory modules. It is very possible that an FSB speed of, say, 1066 MHz only starts to become a bottle neck if you have 4 DRAM banks. An then, for those that have only 2 banks, there would be no measurable effect at all by going to a 1333MHz FSB.