Eight 32 bit cores on one chip for US$13

[sje]

Eight 32 bit cores on one chip for US$13; yes, it's true.

See: http://www.parallax.com/propeller/index.asp

Some limitations:

1) The top speed is only 80 MHz.

2) Only 2 KB of unshared RAM is available per core.

3) A rather limited instruction set; all indexed and indirect addressing can be performed only by first building the appropriate fixed address instruction at run time.

4) Average latency of 15 clocks for a core to access a shared resource.

5) Some parts of the instruction space are not yet implemented; this includes opcodes for "count bits" and "find first bit".

[Dan Andersson]

I like their design decisions. The system is multi core to avoid the usually messy interrupt handling in SoC and micro controllers. And the architecture is symmetric. All Cogs are equal. Decent sized shared RAM (A tad more would have allowed for higher definition graphics output).

Next generation Propeller system is projected to be even beefier:
Eight .times the MIPS per Cog.
Double the number of Cogs.
Quadruple the shared RAM.
Improved I/O.

See monster thread at:
http://forums.parallax.com/forums/defau ... 5&m=156993

MvH Dan Andersson

[sje]

Given that half of the common ROM is reserved for character graphics, I'd say that at least some of the intended application domains are video output related.

On the other hand, being able to substitute reliable polling performance for less predictable interrupt handling points towards real time applications in the automotive and medical device fields.

[Dan Andersson]

The architecture is also a nice fit for robotics. It's easy to see how a subsumption architecture maps right on it.

MvH Dan Andersson

[sje]

Let's say that a third generation Propeller appears and it has much more RAM per core, 64 bit operand length, and lots more I/O pins. And say that it also sells for a low price.

Can you imagine 64 of these hooked together in an 8 by 8 mesh? Each processor would be mapped to one chessboard square, and the cores would handle a bunch of chess calculations specific to that square and its contents. One or two cores would handle general tasks and communications with adjacent chips. Each chip would have global knowledge of the position that that would reduce overall traffic requirements. Altogether, the system would be a kind of super-Belle; both smarter and faster.