Will chess benefit from stacking technology by AMD?

[Thomas Lagershausen]

"AMD CEO Dr. Lisa Su has revealed a prototype AMD Ryzen 9 5900X processor with Zen3 core architecture featuring a DRAM stack on top of the compute tile. This stack is a 3D V-Cache offering an additional 64MB of Level3 cache (SRAM)."

https://videocardz.com/newz/amd-demonst ... let-design

[daniel71]

Actually if I am correct it delivers 64mb per Chiplet, so 3 Chiplets would be be 192mb for the level 3 cache memory increase. On a 64-core processor we are talking about additional 512mb cache memory because there are 8 chiplets. Huge gain for chess but I'm sure someone will disagree with me.

[Ras]

I'm concerned with the thermals of an additional and even heat generating layer between die and heat spreader. It may require lowering the clocks, but increased cache hits may make more than up for this.

[Geonerd]

I thought increasing the L3 / last-level cache produced a limited benefit for most engines. Once the faster caches are large enough to hold all the code, bitboards, etc., the L3 is left buffering hash tables and perhaps tablebase data. And both of those sets are much larger than any sensible L3, so the miss rate is always going to be fairly high.

How does performance scale when comparing smaller, faster hash access to a larger, slower table?

[daniel71]

According to AMD the layers between the silicon will use pure copper increasing thermal and energy efficiency, they will no longer need solder pads between the layers, also cache memory does not produce much heat. TSMC can do up to 12 layers and AMD will only start with 1 layer. The bandwidth from this cache is at 2TB per second much faster than any other interconnect.
Also this is planned for 2022 release so other planned technology will be DDR5 memory, PCIe5 motherboards, SSD 5.0 drives that have announced 14 GB/s read performance. AMD is also expected to have a new node process from .7nm to .5nm. Allowing less heat to be produced better performing cpus using less energy. AMD always tinkers with the microcode increasing amount of instructions per clock cycle. I'm planning to get a new dual processor AMD computer next year.

[toliveanddie76]

According to AMD the layers between the silicon will use pure copper increasing thermal and energy efficiency, they will no longer need solder pads between the layers, also cache memory does not produce much heat. TSMC can do up to 12 layers and AMD will only start with 1 layer. The bandwidth from this cache is at 2TB per second much faster than any other interconnect.
Also this is planned for 2022 release so other planned technology will be DDR5 memory, PCIe5 motherboards, SSD 5.0 drives that have announced 14 GB/s read performance. AMD is also expected to have a new node process from .7nm to .5nm. Allowing less heat to be produced better performing cpus using less energy. AMD always tinkers with the microcode increasing amount of instructions per clock cycle. I'm planning to get a new dual processor AMD computer next year.

kind of sad they are leaving am4 socket behind with this new chip. was hoping for one more generation.

[Geonerd]

kind of sad they are leaving am4 socket behind with this new chip. was hoping for one more generation.

It would make a nice last upgrade for those with a phat DDR4 platform.

[towforce]

It is surprising to me that processor technology is advancing so quickly in 2021.

This branch of technology is devilishly tricky to predict.

August 12 will be the 40th anniversary of the first IBM PC. By today's standards, it was big, slow, expensive, and not very powerful. I would never have guessed that 40 years on, the answer would be, "Same basic processor architecture, but smaller, faster, and with a massive amount of extras on the same dye to make programs run faster".