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I tried to emulate PEXT in software and that runs faster as the native CPU instruction. Do you have a fast implementation that you'd want to make public domain? https://www.chessprogramming.org/BMI2 The serial implementation of PEXT and PDEP look quite similar. Very well possible, but I'm sure I di...

Hi, May 25, 2020 Marcel van Kervinck passed away. Marcel was the developer of Rookie, MSCP and Floyd. From December 2012 until November 2014, he was a member of the board of the CSVN (Dutch computer chess association). There will be a virtual funeral this saturday. Please send me an e-mail if you w...

Gian-Carlo Pascutto wrote: ↑

Fri May 29, 2020 8:40 pm

I tried to emulate PEXT in software and that runs faster as the native CPU instruction.

Do you have a fast implementation that you'd want to make public domain?

https://www.chessprogramming.org/BMI2

The serial implementation of PEXT and PDEP look quite similar.

Move enumeration: 22678 per side considering target square occupancy and disjoint capture target piece. See
https://www.chessprogramming.org/Encodi ... numeration

Often, I test the speed of different function methods. The results indicate the fixed array PushToEdges[] seems to be faster on average: 10 second test ... PushToEdges 16519006400 push_to_edge 16610155136 In a real chess program with many instances fighting for the caches, things may turn out diffe...

Unary minus operator of unsigned integers (short, long) in C/C++ is defined as two's complement, which is the increment of the ones' complement. If you add a value and its ones' complement, the sum has all bits set without any intermediate bitwise overflows. If you further add 1, an overflow occurs ...

Do you remember whether he discussed methods to reduce collisions by improving key independence? Or was it just about measuring the frequency of collisions within real chess trees? Tony Warnock, Burton Wendroff (1988) . Search Tables in Computer Chess . ICCA Journal, Vol. 11, No. 1 Its about BCH Ha...

You are right, there is no r8h (... r15h), only r8l (Intel style) or r8b (MASM STYLE), so one has to use rax, rbx, rcx, rdx with appropriate l/h byte partial registers for that purpose, and maybe ror reg64 16 instead of shift - or better trust the compiler. https://software.intel.com/en-us/articles/...

Turns out that a union is of benefit after all. _DATA SEGMENT bbs STRUCT r1 BYTE ? r2 BYTE ? r3 BYTE ? r4 BYTE ? r5 BYTE ? r6 BYTE ? r7 BYTE ? r8 BYTE ? bbs ENDS bbu UNION bbs<> b64 QWORD ? bbu ENDS occ bbu<> _DATA ENDS _TEXT SEGMENT RayAttacks PROC ; rcx = sq ; rdx = address of rss ; r8 = occ shl ...

Hey Martin and Gerd of course there is the possibility that handwritten assembler would be a benefit. It seems that x86-64 Clang -O3 is hard to beat. The union version prepares many registers with some shift at the beginning to and with 255 aka 16320 = 255 << 6. The explicit shift/and version uses ...