Stockfish 9 ASIC

[Werewolf]

Does anyone have a rough ballpark figure of how much it would cost to develop SF9 (when it comes out) onto an ASIC which would be in a standalone box, able to be plugged into a PC?

I've heard ASIC costs are dropping and one friend was seriously considering raising some cash for this providing it wasn't in millions of dollars.

And any guesses on NPS?

[Leo]

Great to see news efforts being made.

[Milos]

Does anyone have a rough ballpark figure of how much it would cost to develop SF9 (when it comes out) onto an ASIC which would be in a standalone box, able to be plugged into a PC?

I've heard ASIC costs are dropping and one friend was seriously considering raising some cash for this providing it wasn't in millions of dollars.

And any guesses on NPS?

You don't need an ASIC. You can take Xilinx Ultrascale+ Virtex eval board (they are 7k$ per piece). Implement on it movegen, qsearch + eval of SF, and make a version of MCTS SF running on regular PC.
You plug 4 boards in PCIe gen 4 slot. Boards have their own hash.
You easily get 10 million nodes per each of the boards.
So effectively you'd get 40 million MCTS simulations per sec, each of the quality of A0 one.
From Fig 2. of A0 you could get the scaling, but roughly 300-400Elo over A0.
The whole hardware cost 30k$.
Designing power required 5000-10000 man hours or 2-3PY.

[Werewolf]

Does anyone have a rough ballpark figure of how much it would cost to develop SF9 (when it comes out) onto an ASIC which would be in a standalone box, able to be plugged into a PC?

I've heard ASIC costs are dropping and one friend was seriously considering raising some cash for this providing it wasn't in millions of dollars.

And any guesses on NPS?

You don't need an ASIC. You can take Xilinx Ultrascale+ Virtex eval board (they are 7k$ per piece). Implement on it movegen, qsearch + eval of SF, and make a version of MCTS SF running on regular PC.
You plug 4 boards in PCIe gen 4 slot. Boards have their own hash.
You easily get 10 million nodes per each of the boards.
So effectively you'd get 40 million MCTS simulations per sec, each of the quality of A0 one.
From Fig 2. of A0 you could get the scaling, but roughly 300-400Elo over A0.
The whole hardware cost 30k$.
Designing power required 5000-10000 man hours or 2-3PY.

This looks like it requires specialist knowledge though. I was hoping to be able to handover code to a design team (IBM etc) and get them to develop an ASIC.

[Milos]

This looks like it requires specialist knowledge though. I was hoping to be able to handover code to a design team (IBM etc) and get them to develop an ASIC.

Designing digital core in ASIC is for an order of magnitude more complex than on FPGA.

[CheckersGuy]

Does anyone have a rough ballpark figure of how much it would cost to develop SF9 (when it comes out) onto an ASIC which would be in a standalone box, able to be plugged into a PC?

I've heard ASIC costs are dropping and one friend was seriously considering raising some cash for this providing it wasn't in millions of dollars.

And any guesses on NPS?

You don't need an ASIC. You can take Xilinx Ultrascale+ Virtex eval board (they are 7k$ per piece). Implement on it movegen, qsearch + eval of SF, and make a version of MCTS SF running on regular PC.
You plug 4 boards in PCIe gen 4 slot. Boards have their own hash.
You easily get 10 million nodes per each of the boards.
So effectively you'd get 40 million MCTS simulations per sec, each of the quality of A0 one.
From Fig 2. of A0 you could get the scaling, but roughly 300-400Elo over A0.
The whole hardware cost 30k$.
Designing power required 5000-10000 man hours or 2-3PY.

"Each of the qualitiy of A0 "
You throw statements like that around without any justification
That's just impossible to know for now until we get our copies of A0

[Milos]

"Each of the qualitiy of A0 "
You throw statements like that around without any justification
That's just impossible to know for now until we get our copies of A0

If it was like that, any statement would be impossible since A0 would never gonna be released to public.
But ofc it is possible to estimate performance of A0 NN based on Fig. 2 from the paper. A0 crosses SF performance at 400ms/move. That is equivalent to 32000 nodes evaluation. So running MCTS from the paper with qsearch of SF instead of NN and with 32000 qsearches per second vs. SF8 on 64 cores would give us an answer.

[CheckersGuy]

"Each of the qualitiy of A0 "
You throw statements like that around without any justification
That's just impossible to know for now until we get our copies of A0

If it was like that, any statement would be impossible since A0 would never gonna be released to public.
But ofc it is possible to estimate performance of A0 NN based on Fig. 2 from the paper. A0 crosses SF performance at 400ms/move. That is equivalent to 32000 nodes evaluation. So running MCTS from the paper with qsearch of SF instead of NN and with 32000 qsearches per second vs. SF8 on 64 cores would give us an answer.

Implement mcts SF first and show us some benchmarks and then make your point

[Milos]

Implement mcts SF first and show us some benchmarks and then make your point

I'll first get Nature publication then I'll show you results .
I guess it will be enough to show results from the match with SF8 on 1 core, 32MB Hash, no opening book, no EGBT vs MC SF on 32 cores, egbt, 32GB Hash, playing from starting position .

[M ANSARI]

Surely FPGA would be a much better idea. ASIC cannot be updated and for sure SF would need continuous tuning. Also the number of units that would be produced would be very few, thus would make no commercial sense to go ASIC. FPGA has been used in chess engines before and maybe A0 will make this platform interesting again.