Speed of logical ports

[stegemma]

Thinking to try some hardware approach for my engine, I'm searching for information about what could be the fastest device. I've seen that a chip with some logical port could have a propagation time of about 10 ns (or maybe less than this but maybe I could not realize a working board with higher speed). That means that you can reach a maximum of 10M nps, if you use about 10 layers of logical ports in your circuit and if you can compute a single node in a whole. Of course this is light years away from a modern CPU, so there must be something wrong, in my calculation. I suspect that a CPU has very faster logical ports inside with a very faster Tp.

Anybody knows the propagation time of a logical port inside a CPU? And the equivalent ports in a FPGA? (I mean a single whole synthesized logical port)

It seems to me that an hardware approach with simple logical port chips must be done only implementing a strong parallelism, instead it would be less efficient than a generic CPU with standard engine software.

[jdart]

Some interesting discussion here:

http://stackoverflow.com/questions/2909 ... te-cpus-on

One of the issues is that if you are accessing a lot of external memory (like a big hash table) then that may kill whatever speed advantage you could get from a FPGA.

--Jon

[stegemma]

Some interesting discussion here:

http://stackoverflow.com/questions/2909 ... te-cpus-on

One of the issues is that if you are accessing a lot of external memory (like a big hash table) then that may kill whatever speed advantage you could get from a FPGA.

--Jon

Thanks! By reading the discussion that you have proposed, It seems to me that FPGA could be a good choice, for my idea. I keep my doubt about internal logical port speed... but in effect it could be not so important.

[bhamadicharef]

For assessing the speed of port/gates, like you suggest Stefano, you can read the "FPGAs Data Sheet: DC and AC Switching" PDF for each model/family, for e.g. Spartan 6 or Virtex UltraScale.

Timing is few ns (nano second) translating in hundreds of MHz of clock speed. Techniques like adding pipeline allow to increase performance.

Brahim HAMADI CHAREF
Singapore

PS: 2017 should be the year of the FPGA Chess Engine ...

[stegemma]

For assessing the speed of port/gates, like you suggest Stefano, you can read the "FPGAs Data Sheet: DC and AC Switching" PDF for each model/family, for e.g. Spartan 6 or Virtex UltraScale.

Timing is few ns (nano second) translating in hundreds of MHz of clock speed. Techniques like adding pipeline allow to increase performance.

Brahim HAMADI CHAREF
Singapore

PS: 2017 should be the year of the FPGA Chess Engine ...

I think so me too!

I've seen various development kit for FPGA on the net but I'm really confused about which one to choose. Do you have some hint?

Thanks.

[stegemma]

PS: this morning I've buy a MAX 10 lite board; it seems almost complete, for my needs

[bhamadicharef]

I was going to suggest a Xilinx FPGA, but MAX 10 is Altera ! Anyway there are a lot of VHDL or Verilog eBooks to learn programming FPGA. I used VHDL with Vivado and Xilinx Spartan 6 small Papilio, Zynq ZC706 and Ultrascale VCU110. I have been reading a lot of source code from various chess engines and I am focusing on Ethereal from Andrew Grant which I find the easiest to understand and to try to port. UCI will be using a UART. Will update as development progress ...

[stegemma]

I was going to suggest a Xilinx FPGA, but MAX 10 is Altera ! Anyway there are a lot of VHDL or Verilog eBooks to learn programming FPGA. I used VHDL with Vivado and Xilinx Spartan 6 small Papilio, Zynq ZC706 and Ultrascale VCU110. I have been reading a lot of source code from various chess engines and I am focusing on Ethereal from Andrew Grant which I find the easiest to understand and to try to port. UCI will be using a UART. Will update as development progress ...

My choose was only for pratical reason, because I've found an italian reseller for this board, with no extra shipping costs. If you're developing on Xilinx and I will develop on Altera, we can then compare our results on this two different boards. I hope that the project would be portable between multiple FPGA vendors (I wan't use any specific feature of one FPGA).

[matthewlai]

Thinking to try some hardware approach for my engine, I'm searching for information about what could be the fastest device. I've seen that a chip with some logical port could have a propagation time of about 10 ns (or maybe less than this but maybe I could not realize a working board with higher speed). That means that you can reach a maximum of 10M nps, if you use about 10 layers of logical ports in your circuit and if you can compute a single node in a whole. Of course this is light years away from a modern CPU, so there must be something wrong, in my calculation. I suspect that a CPU has very faster logical ports inside with a very faster Tp.

Anybody knows the propagation time of a logical port inside a CPU? And the equivalent ports in a FPGA? (I mean a single whole synthesized logical port)

It seems to me that an hardware approach with simple logical port chips must be done only implementing a strong parallelism, instead it would be less efficient than a generic CPU with standard engine software.

As you have discovered, discrete logic chips will never be as fast as integrated circuits. A modern CPU running at 4GHz means each pipeline stage must only have a delay of 0.25ns. Each pipeline stage usually have a few layers of logic, so we are looking at maybe 50ps delay per logic gate.

The reason is capacitance. Modern logic gates (except in highly specialized applications) are implemented using MOSFETs, which have some capacitance on the gate (input). Every time you want to switch the MOSFET on or off, you have to charge or discharge the capacitance, and that takes time.

When you have gates on a PCB, you have the combined capacitance of the MOSFET, wiring within the chip (to bring it out to the pins/pads), PCB trace, and the output pin of the driving chip. That's a whole lot of capacitance. There's also inductance in the path that stops you from being able to charge quickly, no matter how strong the driver is.

FPGAs are much better, but creating a "gate" on an FPGA still requires a few actual gates (implementing a multiplexer-based look-up table), so with the same process technology, an FPGA design will be about 5x slower than an ASIC design. There's not really a way around that besides making your own chips... and that costs a whole lot of money.

[stegemma]

Oh thanks, now I know why logic port chips are so "slow", compared to embedded ones. I haven't considered capacitance at all. Of course an ASIC is way out my budget but a FPGA with multiple parallel units could competes with modern CPU (I hope).

ps: in chess engine, I mean